1. FIELD OF THE INVENTION
The present invention is related to the field of computer systems, in particular, cache and cache coherency mechanisms.
2. RELATED ART
Traditionally, control of data movement between external devices and the main memory of a computer system is done in either one of two ways. First, data movement can be controlled by the CPU directly reading from the device (to internal CPU registers) or writing from registers to the device. This type of control is called Programmed Input/Output (I/O). The second type of control is with data movement being controlled, for the most part, by the external device itself. This type of control is called Direct Memory Access (DMA), or, if the device accesses memory through virtual addresses, Direct Virtual Memory Access (DVMA). Coordination between the external device and the CPU is typically handled either by message passing or through interrupts.
In many computer systems that employ DMA/DVMA for controlling data movement between the external devices and the main memory, system performance may be improved significantly by including a write back cache for I/O as one of the system elements. However, a problem that can arise from this strategy is maintaining data consistency between the I/O cache and the central cache. Traditional solutions to this problem place the burden of maintaining consistency either on the operating system, which causes severe performance degradation, or on the system hardware, which increases the cost and complexity of the cache design.
Thus, it is desirable to provide a data coherency solution that lessen the burden on the operating system, and yet without significantly increasing the cost and complexity of the cache design. As will be disclosed, this object and desired result is among the objects and desired results of the present invention which provides an optimized hardware and software solution to the data coherency problem between a central cache, a memory and an I/O cache.